Інженер (IC Layout Engineer) групи аналогового дизайну

About the role

The Analog Design Group is looking for an IC Layout Engineer to develop analog topological elements and modules while respecting semiconductor technology constraints. You will collaborate with circuit and layout engineers to ensure high‑performance, area‑efficient designs.

Key responsibilities

• Design analog topological elements/modules considering process, packaging, and circuit constraints.
• Verify layout results against design rules, perform pin placement, parasitic extraction, and topology optimization.
• Ensure DRC, LVS compliance and support tape‑out activities.
• Participate in topology reviews and contribute to floor‑plan definition.
• Work closely with circuit designers to meet speed, area, power, EMC, ESD, and other specifications.
• Prepare and hand over data required for mask generation and semiconductor manufacturing.

Required profile

• University degree in Electrical Engineering or a related field.
• Experience in IC layout (or PCB layout) and analog topology design, preferably with BCD/CMOS technologies.
• Understanding of deep‑submicron effects, parasitics, matching, and power distribution.
• Proficiency in Cadence (or equivalent) tools for layout, DRC, LVS, and extraction.
• Knowledge of analog circuit principles, RC delays, electromigration, and inter‑metal effects.
• Ability to identify unreliable structures and collaborate on optimal solutions.
• English proficiency at B1 level or higher.

Required skills

• Cadence (or similar) layout tools
• DRC and LVS verification
• Parasitic extraction
• Analog circuit design concepts
• BCD/CMOS process knowledge
• Python, SKILL, Perl, TCL, Shell scripting
• Familiarity with Machine Learning/AI concepts

What we offer

• Flexible work schedule with office/home‑office options (hybrid)
• Medical insurance after probation and accident insurance
• Quarterly performance bonus
• 28 calendar days of vacation